The present invention relates to a driver circuit. More particularly, the present invention relates to a driver circuit for differentially outputting data from internal circuitry of an LSI (large scale integrated circuit) to the outside of the LSI.
Recently, multimedia is rapidly becoming widespread. This raises a demand for high-speed, mass data transmission. Therefore, high-speed serial data interfaces such as IEEE1394 and Gigabit Ethernet(copyright) have attracted attention. In these interface technologies, a driver circuit differentially transmits data from internal circuitry of an LSI at a high speed such as 1 Gbit/s. As shown in FIG. 8, this driver circuit forms a current mirror by applying a bias voltage Vbn generated by a reference current circuit to the gate of a MOS (Metal Oxide Semiconductor) transistor M50, and generates a desired, constant drive current. Either a differential output terminal TD or NTD to which the drive current is to be applied is determined by MOS transistors M51, M52, whereby the driver circuit digitally drives a prescribed current. This drive current is driven to a receiving device as a desired output voltage through resistors R respectively connected to the output terminals TD, NTD.
If the output differential data from the driver circuit of FIG. 8 do not cross at the center, a differential skew (difference between the respective medians of the differential data) is generated as shown in FIG. 9. A large differential skew would increase variation in cross point in the time direction when the drive current varies due to noises or the like. As shown in FIG. 10, provided that the differential data ideally cross at the center, the intersection p1 is shifted to p2 or p2xe2x80x2 as the gradient of the voltage with respect to time is varied. If there is a difference in switching time, t_diff, the intersection q1 is shifted to q2 or q2xe2x80x2 as the gradient is varied. Therefore, it can be appreciated that, provided that variation in gradient is the same, the displacement of the intersection with respect to time, i.e., (p2xe2x88x92p1) or (q2xe2x88x92q1), is increased if there is a difference in switching time. That is, (p2xe2x88x92p1) less than (q2xe2x88x92q1). Accordingly, in a differential driver, variation in switching timing would increase jitter components of the time direction due to noises or the like, thereby causing reduction in margin for communications. Note that the difference in switching time, t_diff, is negative, the displacement of the intersection with respect to time is seemingly reduced. In the subsequent cycle, however, the differential potentials rise and fall in the opposite manner, whereby the difference t_diff becomes positive. In view of irregular disturbance such as noises, it is ideal to make the differential data cross at the center.
It is an object of the present invention to provide a driver circuit allowing complementary output data to cross at an appropriate position (near the center).
According to one aspect of the present invention, a driver circuit includes a constant current section, a first pad, a second pad, a first switching element, a second switching element and a control section. The constant current section outputs a prescribed positive or negative current. The first pad is capable of being connected to the other end of a first resistor having its one end connected to a first node receiving a first voltage. The second pad is capable of being connected to the other end of a second resistor having its one end connected to the first node. The first switching element is connected between an output node of the constant current section and the first pad and turned ON/OFF in response to a first signal. The second switching element is connected between the output node of the constant current section and the second pad and turned ON/OFF in response to a second signal. The second signal is complementary to the first signal. The control section controls a potential at the output node of the constant current section to a prescribed potential.
According to another aspect of the present invention, a driver circuit includes a constant current section, a first pad, a second pad, a first switching element, a second switching element, a first resistor, a second resistor and a control section. The constant current section outputs a prescribed positive or negative current. The first switching element is connected between an output node of the constant current section and the first pad and turned ON/OFF in response to a first signal. The second switching element is connected between the output node of the constant current section and the second pad and turned ON/OFF in response to a second signal. The second signal is complementary to the first signal. The first resistor is connected between a first node receiving a first voltage and the first pad. The second resistor is connected between the first node and the second pad. The control section controls a potential at the output node of the constant current section to a prescribed potential.
In the above driver circuit, the control section controls the potential at the output node of the constant current section to the prescribed potential regardless of variation in voltage and variation in process. This suppresses variation in ON/OFF timing between the first and second switching elements. This allows differential data from the first and second pads to cross at an appropriate position (near the center).
Preferably, the control section varies an on-state resistance value of the first and second switching elements according to the potential at the output node of the constant current section.
In the above driver circuit, the potential at the output node of the constant current section reduces with increase in on-state resistance value of the first and second switching elements, and increases with reduction in on-state resistance value of the first and second switching elements. The control section therefore increases the on-state resistance value of the first and second switching elements when the potential at the output node of the constant current section is higher than a desired potential, and reduces the on-state resistance value of the first and second switching elements when the potential at the output node of the constant current section is lower than the desired potential. The control section thus controls the potential at the output node of the constant current section to the prescribed potential.
Preferably, the first switching element includes a first transistor. The first transistor is connected between the output node of the constant current section and the first pad and turned ON/OFF in response to the first signal. The second switching element includes a second transistor. The second transistor is connected between the output node of the constant current section and the second pad and turned ON/OFF in response to the second signal. The control section varies a substrate potential of the first and second transistors according to the potential at the output node of the constant current section.
In the above driver circuit, if the first and second transistors are of NMOS type, the on-state resistance increases with reduction in substrate potential of the first and second transistors and reduces with increase in substrate potential. If the first and second transistors are of PMOS type, the on-state resistance varies in the manner opposite to that described above. Provided that the first and second transistors are of NMOS type, the control section reduces the substrate potential of the first and second transistors when the potential at the output node of the constant current section is higher than a desired potential. This increases the on-state resistance value of the first and second transistors and reduces the potential at the output node of the constant current section. On the other hand, when the potential at the output node of the constant current section is lower than the desired potential, the control section increases the substrate potential of the first and second transistors. This reduces the on-state resistance value of the first and second transistors and increases the potential at the output node of the constant current section. The control section thus controls the potential at the output node of the constant current section to the prescribed potential.
Preferably, the first switching element includes a first transistor and a second transistor. The first and second transistors are connected in parallel between the output node of the constant current section and the first pad and turned ON/OFF in response to the first signal. The second switching element includes a third transistor and a fourth transistor. The third and fourth transistors are connected in parallel between the output node of the constant current section and the second pad and turned ON/OFF in response to the second signal. The control section activates and inactivates the first to fourth transistors according to the potential at the output node of the constant current section.
In the above driver circuit, the first switching element has a greater on-state resistance value when either the first or second transistor is ON than when both the first and second transistors are ON. Similarly, the second switching element has a greater on-state resistance value when either the third or fourth transistor is ON than when both the third and fourth transistors are ON. Therefore, when the potential at the output node of the constant current section is higher than a desired potential, the control section activates one of the first and second transistors and inactivates the other transistor. In other words, the control section turns ON/OFF either the first or second transistor in response to the first signal. Similarly, the control section activates one of the third and fourth transistors and inactivates the other transistor. In other words, the control section turns ON/OFF either the third or fourth transistor in response to the second signal. The on-state resistance of the first and second switching elements is thus increased. On the other hand, when the potential at the output node of the constant current section is lower than the desired potential, the control section activates both the first and second transistors. In other words, the control section turns ON/OFF both the first and second transistors in response to the first signal. Similarly, the control section activates both the third and fourth transistors. In other words, the control section turns ON/OFF both the third and fourth transistors in response to the second signal. The on-state resistance of the first and second switching elements is thus reduced. In this way, the control section controls the potential at the output node of the constant current section to the prescribed potential. The above driver circuit is capable of digitally varying the on-state resistance value of the first and second switching elements. This eliminates the need to generate an analog bias potential and thus facilitates circuit design.
Preferably, the prescribed potential is set to a value close to an intermediate potential of minimum and maximum values of a gate potential of the first or second transistor minus a threshold potential of the first or second transistor.
The above driver circuit allows the transistors included in the first switching element and the transistors included in the second switching element to be accurately turned ON/OFF at the same timing.
According to still another aspect of the present invention, a driver circuit for complementarily driving first and second output nodes in response to differential input signals includes a first driving section, a second driving section and a control section. The first driving section drives the first output node in response to one of the differential input signals. The second driving section drives the second output node in response to the other differential input signal. The control section controls timing of driving the first and second driving sections so that voltage levels at the first and second output nodes switch at the same timing.
The above driver circuit suppresses variation in switching timing of the voltage level between the first and second output nodes. This allows differential data from the first and second output nodes to cross at an appropriate position (near the center).